Date: Wed, 20 Nov 1996 22:33:20 GMT
Server: Apache/1.0.3
Content-type: text/html
Content-length: 2663
Last-modified: Tue, 08 Oct 1996 19:40:04 GMT

<TITLE>B441/B541 Digital Hardware Design, Fall 1996</TITLE>
<H1>B441/B541 Digital Hardware Design, Fall 1996</H1>
<HR>
<H2>Instructor</H2>
<!WA0><A HREF="http://www.cs.indiana.edu/hyplan/prosser.html">
Franklin Prosser</A>
<UL>
<LI> T noon-12:45, W 10:30-11:30, and by arrangement and by
drop-in. All in LH330E.
</UL>

<H2>Associate Instructors</H2>
<UL>
<LI><!WA1><A HREF="http://www.cs.indiana.edu/hyplan/davwils.html">David Wilson</A>
<UL>
<LI> T noon-1, W 10-11
</UL>
</UL>
<UL>
<LI><!WA2><A HREF="http://www.cs.indiana.edu/hyplan/rudesai.html">Rutvik Desai</A>
<UL>
<LI> TR 4.00-5.00 
</UL>
</UL>



<h2>Texts for Fall 1996 </h2>

** <a name="Prosser/Winkel">Franklin Prosser and David Winkel, <em>The Art of
Digital Design,</em> printed by IU Bookstore.</a> <br><br>

** Additional documents for the laboratory will be distributed in class and
lab, or are available <!WA3><A HREF="http://www.cs.indiana.edu./classes/c421-wein/man/man.html">online.</A> <br>


<h2>Newsgroup</h2>

The newsgroup for B441/B541 is <em>ac.csci.b441</em> on the computer science
departmental network. Check this newsgroup regularly. It will be used for a
variety of announcements, and may be used by everyone to make and respond to
course-related inquiries and post interesting tidbits.


<br> <br> <h2> Lecture schedule.</h2>

<pre>
Lect.	Topics and Prosser/Winkel sections
<hr>

1 1/2	Boolean algebra, Karnaugh maps (Ch. 1)

2 1/2	Mixed logic (Ch. 2)

1	Open-collector circuits (Ch. 2)

1 1/2	Combinational building blocks: multiplexer, decoder, adder, etc. (Ch. 3)

1 1/2	Speed-up of addition; busses (Ch. 3)

1 1/2	Hazards, RS flip-flop (Ch. 4)

2	Clocked storage elements: JK flip-flop, counters, shifters, etc. (Ch. 4)

1	Building counters

1	Data sheets (Ch. 12)

2	ASMs and state generators (Ch. 5)

1	Clock skew, races, and other headaches (Ch. 5)

2 1/2	Design examples: single pulser, traffic controller, etc. (Ch. 6)

3 1/2	Design examples: serial bit clock, serial-parallel conversion (Ch. 6)

2 1/2	Additional topics, course administration, or extra review
</pre>
<br>
<br>

<H2>Grading:</H2>
<UL>
<LI>3 in-class examinations @ 20%
<LI>Laboratory @ 35%
<LI>Class Homework @ 5%
</UL>

<EM>Note:</EM> Assignments not ready by lecture time may be slipped into the
departmental drop box by 5:00 PM on the date due. To be sure of proper
delivery, place (AI's) name on the assignment. </P>
<br>

<H2>Laboratory</H2>

Click <!WA4><A
HREF="http://www.cs.indiana.edu./classes/b441/b441-lab-syllabus.html">here</A>
to see the laboratory schedule and other useful lab information. <br><br>

====================================================================== 
<br><br>

prosser/27Aug96


















